1. Field of the Invention
The present invention relates to semiconductor devices and, more particularly, to ternary content addressable memory (CAM) cells.
2. Description of the Related Art
Random access memory (RAM) devices merely have functions to store and read out data. However, there have recently been many demands on semiconductor devices such as CAM devices having a function to compare the data stored in the RAM device with an external signal (search signal) as well as a function of the RAM device. A unit cell of the CAM includes at least one storage cell and a match cell. The storage cell corresponds to a typical memory cell such as an SRAM cell. Also, the match cell compares the data stored in the storage cell with the search signal and outputs an electrical signal that corresponds to the comparison result.
The CAM can be classified into a binary CAM and a ternary CAM. The binary CAM discriminates whether the data stored in the storage cell coincides with a search signal (hereinafter, referred to as “search data”) or not. That is, the binary CAM has a function of which determines only two cases.
Examples of the binary CAM are taught in U.S. Pat. Nos. 4,646,271, 4,780,845, 5,490,102 and 5,495,382.
In the meantime, the ternary CAM typically includes two storage cells and a single match cell. The ternary CAM exhibits three kinds of output states according to the combination of the data stored in the pair of storage cells. That is, the ternary CAM may have a “don't care” state in addition to a match state and a non-match state. The ternary CAM is taught in U.S. Pat. No. 5,319,590, entitled “Apparatus for storing ‘DON'T CARE’ in a content addressable memory cell”, the teachings of which are incorporated herein by reference.
FIG. 1 is an equivalent circuit diagram of the ternary CAM cell disclosed in the U.S. Pat. No. 5,319,590.
Referring to FIG. 1, the ternary CAM cell includes first and second storage cells 301 and 302, and a single match cell 102. Further, the ternary CAM cell includes two sets of bit lines /BL1, BL1, BL2, and /BL2. The first set of the bit lines /BL1 and BL1 are connected to the first storage cell 301 through access transistors 303 and 304 respectively, and the second set of the bit lines BL2, /BL2 are connected to the second storage cell 302 through access transistors 305 and 306 respectively. Gate electrodes of the access transistors 303, 304, 305 and 306 are connected to a word line.
The match cell 102 is composed of first to fourth transistors 102a, 102b, 102c and 102d. The first and second transistors 102a and 102b are serially connected, and the third and fourth transistors 102c and 102d are also serially connected. Drain regions of the first and third transistors 102a and 102c are connected to a match line MV, and source regions of the second and fourth transistors 102b and 102d are grounded. Further, gate electrodes of the first and third transistors 102a and 102c are connected to first and second search lines /ML, ML respectively, and gate electrodes of the second and fourth transistors 102b and 102d are connected to a data storage node al of the first storage cell 301 and a data storage node a2 of the second storage cell 302 respectively. The match line MV is generally pre-charged in a standby mode, thereby having a logic “1” state.
In this circuit, if data corresponding to a logic “0” is stored in the storage node al and a signal corresponding to a logic “1” is applied to the search line /ML, the voltage level of the match line MV may be unstable. This is because the drain region of the second transistor 102b (that is, the source region of the first transistor 102a) floats.
Embodiments of the invention address these and other limitations of the prior art.